Current gate electrodes suffer from undesirable parasitic overlap capacitance at the gate edge.
U.S. Pat. No. 5,998,288 to Gardner et al. describes an etch back of an oxide spacer 22 that does not continue the etch back to the gate dielectric layer.
U.S. Pat. No. 5,864,160 to Buynoski describes a gate with an air gap on one side and a sealing step.
U.S. Pat. No. 6,015,746 to Yeh et al. describes an air gap on the sides of a gate.
U.S. Pat. No. 5,770,507 to Chen et al. describes an air gap on the side of a gate.
U.S. Pat. No. 5,972,763 to Chou et al. describes formation of an air gap spacer of a metal-oxide semiconductor device.
Accordingly, it is an object of the present invention to provide a method of forming an air-gap under the edges of a gate electrode.
Another object of the present invention is to provide a method of reducing parasitic overlap capacitance at the gate electrode edge.
A further object of the present invention to provide a method of forming an air-gap under the edges of a gate electrode to reduce parasitic overlap capacitance at the gate edge.
Yet another object of the present invention is to provide a method of forming an air-gap under the edges of a gate electrode to reduce parasitic overlap capacitance at the gate edge by using conventional processes.
Another object of the present invention to provide a method of forming an air-gap under the edges of a gate electrode without adversely affecting the isolation oxide.
Other objects will appear hereinafter.
It has now been discovered that the above and other objects of the present invention may be accomplished in the following manner. Specifically, a semiconductor substrate having at least a pair of STIs defining an active region is provided. A gate electrode is formed on the substrate within the active region. The gate electrode having an underlying gate dielectric layer. A liner oxide layer is formed over the structure, covering the sidewalls of the gate dielectric layer, the gate electrode, and over the top surface of the gate electrode. A liner nitride layer is formed over the liner oxide layer. A thick oxide layer is formed over the structure. The thick oxide, liner nitride, and liner oxide layers are planarized level with the top surface of the gate electrode, and exposing the liner oxide layer at either side of the gate electrode. The planarized thick oxide layer is removed with a portion of the liner oxide layer and a portion of the gate dielectric layer under the gate electrode to form a cross-section inverted T-shaped opening on either side of the gate electrode. A gate spacer oxide layer is formed over the structure at least as thick as the gate electrode, wherein the gate spacer oxide layer partially fills the inverted T-shaped opening from the top down and wherein air gap spacers are formed proximate the bottom of the inverted T-shaped opening. The gate spacer oxide, liner nitride, and liner oxide layers are etched to form gate spacers proximate the gate electrode. The gate spacers having an underlying etched liner nitride layer and liner oxide layer.